The present invention is generally directed to improved methods and apparatus for controlling the timing of signals provided on an integrated circuit (IC) chip.
As is well known, in designing digital logic circuitry for use on an IC chip, there often arises a need for additional timing edges besides those provided by a standard system clock. This is particularly true for IC chip designs which utilize memory structures (RAM, ROM, etc.). These additional timing edges may typically take the form of clocks which are required to switch at times other than the standard system clock.
The need to provide these additional timing edges creates a problem with respect to IC chips, particularly VLSI (very large scale integrated) circuit chips where it is desirable to compact as much as possible onto the chip. This problem arises because of the difficulties involved in accurately providing such additional timing edges on a VLSI chip.
Typically, additional timing edges are provided on an IC chip by delaying the standard system clock by a prescribed amount using serially-connected inverters or other active delay elements formed on the chip. These active on-chip delays are severely affected by unpredictable processing variations as well as by voltage and temperature, which can cause the resulting delay to vary by as much as .+-.60%. Thus, when a large delay is required to be provided on an integrated circuit chip, this .+-.60% variation may not be tolerable. A typical known solution is to provide this required long delay circuitry off-chip where accuracy can be more precisely controlled. However, this has the severe disadvantage of requiring more parts, more board space, and more expense.
An example of the problem associated with providing a relatively long on-chip delay on an IC chip is illustrated by the graphs in FIG. 1.
Graph A in FIG. 1 illustrates a typical standard system clock C having a clock cycle time T with rising clock edges occurring at times T1 and T3, and falling clock edges occurring at times T2 and T4.
Graph B in FIG. 1 illustrates a FIRST DELAYED CLOCK C1 produced by an on-chip delay d1 providing a relatively small delay (e.g., d1=0.10 T). It is assumed in Graph B that d1 varies by about .+-.40% of d1, as indicated by .DELTA.d1.
Graph C in FIG. 1 illustrates a SECOND DELAYED CLOCK C1 produced by an on-chip delay d2 providing a relatively large delay (e.g., d2=0.90 T). Similar to d1 in Graph B, it is assumed in Graph C that d2 varies by about .+-.40% of d2, as indicated by .DELTA.d2.
As shown by Graph B in FIG. 1, the effect of .DELTA.d1 on the timing edges provided by C1 is relatively small and can easily be tolerated. This will be evident by noting that, for d1=0.10 T, .DELTA.d1 will only amount to about 0.08 T.
However, as shown by Graph C in FIG. 1, the effect of .DELTA.d2 on the timing edges of C2 is intolerable, since it can cause the rising edge of C2 to occur in the next clock cycle (after T3). This will be evident by noting that, for d2=0.90 T, .DELTA.d2 will amount to about 0.72 T. This will cause the rising clock edge of C2 to occur at about 1.26 T (0.90 T+0.36 T), which is greater than the clock cycle time T, as illustrated in Graph C. Note that this occurred assuming that .DELTA.d2 varies by .+-.40% Since this variation may typically be .+-.60% in the worst case, the provision of other than relatively small delays on a chip can present a serious problem. This is a primary reason why the prior art normally provides relatively long delays (such as those greater than T/2) off-chip where delay variations can be better controlled.